The present invention relates to a method of forming low-resistivity connections in a non-volatile memory and to a memory with low-resistivity connections formed by the method.
To give an example of a typical field of use of the invention, a known programmable non-volatile memory (EPROM) structure formed on a monocrystalline silicon substrate with p conductivity is described below with reference to FIGS. 1 and 2. The invention is intended, however, to be applied advantageously to any type of non-volatile memory which requires low-resistivity connections.
FIG. 1 shows in plan a portion of a memory matrix which contains ten cells arranged in two rows and five columns and FIG. 2 is a section taken on the line IIxe2x80x94II of FIG. 1 through two cells of a column.
In the following description, the direction of the rows will be defined as horizontal and the direction of the columns will be defined as vertical. The active regions, that is, the regions of the substrate which are separated from one another by thick oxide (field oxide) are indicated by hatching.
Two cells of the same column have their drain regions, indicated D, in common, and their source regions, indicated S, connected to the source regions of the cells belonging to the same row by regions, indicated R, which are formed in the substrate simultaneously with the source and drain regions by diffusion of n-type impurities. Floating gate electrodes of doped polycrystalline silicon, indicated FG, are formed on two regions disposed above the channels which separate the source and drain regions of each cell, and are insulated from the substrate by respective thin layers of gate oxide. Strips CG of doped polycrystalline silicon comprising the control gate electrodes of the EPROM cells extend horizontally above the floating gate electrodes FL, which are insulated therefrom by an oxide layer I1. Metal strips M1G, shown as defined between broken lines in FIG. 1, extend horizontally above the control gate strips CG of each row, and are insulated therefrom by an oxide layer I2. Interconnection elements V1 which extend through the oxide layer I2 put the metal strips M1G into contact with the underlying polycrystalline silicon strips CG. A further oxide layer I3 covers the metal strips M1G.
Source metal strips SL extend vertically on the insulating layer I3 and are in contact with the diffused regions R connecting the source regions S of the cells of the various rows by means of interconnection elements which extend through the dielectric material of the various superimposed insulating layers I3, I2, I1 and are shown in FIG. 1 by small squares indicated V2. The vertical metal strips SL are spaced apart horizontally by predetermined distances and are connected together, in a manner not shown, to a common terminal which is usually the lower-potential terminal of the integrated circuit in which the memory matrix is formed.
Metal drain strips M2D extend vertically on the insulation layer I3 and each is in contact with the drain regions D of the cells of a column by means of interconnection elements which are similar to those between the strips SL and the regions R, and each of is which shown in plan (FIG. 1) by a small square indicated V3 and in section (FIG. 2) by three superimposed conductive elements, that is, a column V31, a connector V32, and an interconnection via V33.
The gate metal strips M1G constitute the word lines (WLi) of the matrix and the drain metal strips M2D constitute the bit lines (BLi) of the memory matrix, whilst the metal strips SL constitute the connections of the source regions of the cells to the common source terminal.
Briefly, to produce the structure shown, a layer of polycrystalline silicon is deposited on a thin layer of gate dielectric (silicon dioxide formed on the surfaces of the active regions by thermal oxidation). The polycrystalline silicon layer is etched by usual photolithography techniques to define the polycrystalline silicon floating gate electrodes FL, which are separated from the substrate by the gate dielectric. Ions of a doping element with n conductivity are implanted in the portions of the substrate which are not covered by the floating gate electrodes FL to form the source regions S and the drain regions D of the cells and the regions R joining the source regions and to dope the polycrystalline silicon of the floating gate electrodes FL. A layer of silicon dioxide (I1) is deposited, followed by a second layer of doped polycrystalline silicon. This second polycrystalline silicon layer is also etched by usual photolithography techniques to define the horizontal strips CG which contain the control gate electrodes of the cells. A second silicon dioxide layer (I2) is deposited, contact areas are opened up in predetermined positions of the layer, more precisely, on the diffused regions R, on the drain regions D, and on the strips CG. A layer of metal, for example, tungsten, is deposited and selectively removed to form the lower portions of the interconnection elements V2 and V3, amongst which are the columns V31. A layer of metal, for example, aluminum, is then deposited on the silicon dioxide layer I2 and on the portions of the underlying polycrystalline silicon strips CG which are exposed by the contact areas, thus forming the interconnection elements V1, and the horizontal metal strips M1G and the connections V32 are formed by photolithography. A third silicon dioxide layer I3 is deposited, contact areas are opened up through the oxide layer I3, and a second metal layer, for example, aluminum again, is then deposited and forms the interconnection vias V33. The source interconnection strips SL and the drain interconnection strips M2D are formed by photolithography from this second metal layer.
The horizontal metal strips M1G have the function of connecting the respective polycrystalline silicon strips which form the control gate electrodes of the cells of each row to corresponding external terminals (not shown) of the matrix of cells by a low-resistivity path, as will be explained further below, and constitute the word lines WLi. The vertical metal strips M2D have the function of interconnecting the drain terminals of the cells of the columns of the matrix and constitute the bit lines BLi. The vertical metal strips SL have the function of connecting the source regions of all of the cells to a common terminal.
When the memory is in operation, currents pass through both the polycrystalline silicon strips CG of the control gate electrodes and the regions R joining the source regions. These currents cause voltage drops which depend on the resistivities of the materials of which the strips CG and the regions R are made. Memory cells which are disposed at different distances from a terminal of the matrix are therefore biased differently. The resistivities are fixed by design criteria which cannot generally be changed. In practice it is therefore necessary to arrange the contacts V1 between the polycrystalline silicon strips CG and the metal strips M1G as well as the contacts V2 between the regions R joining the source regions and the source connection strips SL, at distances such as to render the voltage drops negligible. However, the contacts need to occupy area on the substrate. The overall area occupied by the contacts is larger the larger are the dimensions of the memory matrix. Since the tendency at the moment is to design memories of ever greater capacity on ever smaller areas, there is a great need for novel structures and novel methods of forming low-resistivity connections.
In order to reduce the resistivity of the connections, it is known to treat the monocrystalline or polycrystalline silicon surfaces by depositing on them thin layers of metals which can react with the silicon, forming silicides, when they are heated to a relatively high temperature. However, these techniques are quite difficult when the surfaces to be treated have very small dimensions or have raised portions, as in the case of very highly integrated non-volatile memories formed by a method such as that described above.
The invention provides an improved method for reducing the resistivity of connections within a semiconductor chip. It is particularly helpful for non-volatile memories. A structure according to the method is also provided.
The method applies to semiconductor memories with cells arranged in rows and in columns, in which each cell has a first terminal, a second terminal, and a third terminal connected, respectively, to a row line, to a column line, and to a common node by respective connection strips. In order to form connections with low resistivity and to save semiconductor area, the method provides for the formation of an oxide layer which covers the connection strips of the first terminals and of the third terminals, the formation of channels along the connection strips until the surfaces thereof are exposed, and the filling of the channels with a material having a resistivity lower than that of the connection strips.